module regfile(
    input  logic        clk,
    input  logic        regWriteEn,
    input  logic [4:0]  regwriteaddr, Rsaddr, Rtaddr,
    output logic [31:0] regwritedata, Rsdata, Rtdata);
 logic [31:0] rf[31:0];

 always @(posedge clk)
    if(regWriteEn)  rf[regwriteaddr] <= regwritedata;
    assign Rsdata = (Rsaddr != 0) ? rf[Rsaddr] : 0;
    assign Rtdata = (Rtaddr != 0) ? rf[Rtaddr] : 0;

endmodule